1. Field of the Invention
The present invention pertains to the precision surface machining of semiconductor wafers, and in particular to chemical/mechanical polishing (CMP) of silicon and other types of semiconductor wafers.
2. Description Of The Related Art
In the commercial production of semiconductor wafers, a semiconductor wafer undergoes successive operations in which relatively thin layers of conductive, semiconductive and dielectric materials are formed on one of the wafer's major surfaces by metalization, sputtering, ion implantation and other conventional techniques. Although the thicknesses of such layers is measured in terms of microns or micro inches, the exposed surfaces must be polished flat, in preparation for successive layering operations.
The SpeedFam Corporation of Chandler, Ariz., Assignee of the present invention, manufactures a variety of equipment for planarizing and otherwise preparing wafer surfaces using a variety of techniques, including chemical/mechanical polishing (CMP) processes. Typically, the layered surface (device side) of the wafer is placed face down on the polish pad carried on a rotating table or incorporated in a linear belt. A chemically active media which may also contain abrasive particles is introduced onto the polish table and migrates between the wafer and the polish pad. A carrier and compressible backing pad apply a downforce to the back side of the wafer, pressing the device side of the wafer against the polishing pad surface. Typically, the polish pad is made considerably larger than the diameter of the wafer being polished. The carrier applying downforce to the wafer is rotatably driven about a vertical axis so as to rotate the wafer with respect to the moving polish pad surface, thereby increasing the relative motion between the wafer and the polish pad. Typically, the carrier and hence the wafer is also reciprocated back and forth along an arc, usually intersecting a radial line originating at the center of the polish pad.
In order to maintain the wafer underneath the carrier despite sideways or lateral dislodging forces, a retaining ring sometimes called a "polishing ring", dimensioned to loosely surround the wafer, travels with the carrier, with the wafer being held captive within the retaining ring. The retaining ring is thereby held in close relationship and oftentimes in contact relationship with the polish pad surface, which inevitably affects the flow of slurry between the wafer and polish pad surface.
It has been observed in commercial wafer polishing operations that despite precautions to the contrary, the material removal rate is not uniform across the wafer surface. For example, even though the wafer carrier is made relatively flat and rigid so as to apply a uniform downforce throughout the wafer back side surface, the outer annular edge regions of the wafer show evidence of an increased material removal compared to the inner portions of the wafer, a so-called "over-polishing" condition. This introduces wafer non-uniformities such as deviations from wafer global uniformity. Further, the wear at the edge region of the wafer is increased to the point where devices located in the edge region may undergo substantial degradation. There is an increasing emphasis among manufacturers of semiconductor devices that the total area of such degradation ("edge exclusion") be reduced. As semiconductor devices become larger, edge exclusion is more likely to play a role in reducing the number of devices that can be obtained from a semiconductor wafer.
Several attempts at reducing edge over polish have been attempted. For example, polishing operations employing retaining rings have been made to apply an added downforce to the retaining rings sufficient to partly compress the polish pad, thus locally deflecting the polish pad beneath the edge region of the wafer being polished. In another proposed arrangement, U.S. Pat. No. 5,573,448 provides a recess or groove in the backing pad at the outer periphery of the wafer. The recess, however, allows the slurry to become trapped, thereby modifying the downforce on the wafer being polished, in an angularly non-uniform manner, again leading to global irregularities in the wafer surface. Further, U.S. Pat. No. 5,573,448 is directed to use of a polishing template in which multiple wafer, held by a common template, are polished at the same time. The wafers and template together form a polishing system in which local forces and excursions within the system are transmitted to other parts of the system, with a polishing of one wafer being affected by another in a time varying manner as the polishing operation is being carried out. Improvements in wafer polishing are continually being sought.